Microprocessor breakpoint apparatus

ABSTRACT

A breakpoint apparatus incorporated in a single chip microprocessor. The apparatus permits breakpoints on specific references to either program instructions or data. The width of the breakpoint address can be varied, the apparatus includes a logic circuit for determining if the reference represented by the breakpoint address overlaps the current virtual address.

This is a continuation of application Ser. No. 07/703,676, filed May 20,1991 .Iadd.now U.S. Pat. No. 5,165,027.Iaddend., which is a continuationof application Ser. No. 07/593,399, filed Oct. 3, 1990, now U.S. Pat.No. 5,053,944, which is a continuation of application Ser. No.07/370,024, filed Jun. 22, 1989, now abandoned, which is a continuationof application Ser. No. 07/274,636, filed Nov. 15, 1988, now U.S. Pat.No. 4,860,195, which is a continuation of application Ser. No.06/822,263, filed Jan. 24, 1986, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of hardware implemented breakpointsfor computer programs, primarily used for analyzing or "debugging"programs.

2. Prior Art

Numerous techniques are used to analyze the performance of computerprograms, particularly during their development. This is often referredto as "debugging". The debugging process is recognized as a significantpart of the development of a computer program, and in some cases, thetime required for debugging exceeds that required to write the program.

One technique used for debugging computer programs is to interrupt theprogram at predetermined events and then examine, for instance, thecontents of registers. One such event is the generation of predeterminedaddresses which may be references to the computer program or data. Whenthe address generated by the computer matches one of the predeterminedaddresses, a "breakpoint" occurs. The operation of the computer isinterrupted to permit analysis.

One method of providing a breakpoint interrupt is to modify the computerprogram itself. At certain addresses in the program, the programprovides an interrupt. This method is relatively inexpensive, however,it has the disadvantage that breakpoints cannot be set for addressreferences to data.

In another method, hardware external to the computer or microprocessoris used for breakpoint interrupts. This hardware compares the computergenerated addresses with the predetermined addresses and provides abreakpoint, or interrupt signal. This method is generally expensive andrequires a significant amount of printed circuit board space. Moreover,for high speed processors it does not react quickly enough to provide a"real time" breakpoint. A significant problem arises wheremicroprocessor includes an address translation unit such as a memorymanagement unit on the microprocessor itself. The only computergenerated addresses accessible to a user are the physical addressestypically communicated to a random-access memory. That is, virtualaddresses used by the programmer may not be available. It is difficultto set breakpoints based on physical addresses.

As will be seen, the present invention provides a breakpoint apparatuswhich solves the above problems, and moreover, provides enhancedbreakpoint selection.

SUMMARY OF THE INVENTION

The present invention provides a breakpoint signal apparatus useful indebugging computer programs. The apparatus is particularly useful in anintegrated circuit microprocessor formed on a single substrate whichincludes address generation means for generating virtual addresses forreference to program instructions or data, a virtual address bus,address translation means for converting the virtual address on the busto a physical address, interpretation means for interpreting the programinstructions, and arithmetic means for operating upon the data inaccordance with the interpreted instructions. The apparatus includes afirst register for storing a predetermined address in the form of avirtual address at which a breakpoint is to occur. A second register isused for storing control bits which permit the user to select certainconditions of the breakpoint such as whether the breakpoint is to occurat a reference to computer program or data. a comparator means comparesthe predetermined virtual address with the address generated by thecomputer (current virtual address). A first logic means determines ifthe current virtual address is a reference to program instructions ordata by examining address control signals. This logic means is alsocontrolled by the control bits stored in the second register. Gatingmeans used to provide the breakpoint signal and interrupt the operationof the computer is coupled to the output of the comparator means and thefirst logic means. The entire apparatus is formed on the same substratewith the microprocessor.

The apparatus also includes second logic means to determine if thecurrent virtual address falls within the reference represented by thepredetermined address or if the reference represented by thepredetermined address falls within the reference made by the virtualaddress. In effect, this permits the width of the predeterminedbreakpoint address to be set by control bits stored in the secondregister.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the overall microarchitecture ofa microprocessor in which the apparatus of the present invention isused.

FIG. 2 is a block diagram illustrating the breakpoint apparatus of thepresent invention.

FIG. 3 is an electrical schematic of one stage of one of the registersused in the block diagram of FIG. 2.

FIG. 4a is a diagram used to illustrate the case where the memoryreference represented by the predetermined (breakpoint) address is widerthan a memory address reference.

FIG. 4b is a diagram used to illustrate the case where the memoryreference represented by the predetermined (breakpoint) address isnarrower than a memory address reference.

DETAILED DESCRIPTION OF THE INVENTION

A breakpoint apparatus is described which is particularly suitable foruse in a microprocessor where the microprocessor includes an addresstranslation unit integrally fabricated with the microprocessor.Typically in such cases, the virtual addresses are not accessible to theuser making it difficult to set breakpoints. In the currently preferredembodiment, the breakpoint apparatus is integrally formed on the samesubstrate with the microprocessor and its address translation unit.

In the following description, numerous specific details are set forth,such as specific number of bits, etc., in order to provide a thoroughunderstanding of the present invention. It will be obvious, however, toone skilled in the art that the present invention may be practicedwithout these specific details. In other instances, well-knownstructures are not shown in detail in order not to unnecessarily obscurethe present invention.

In its currently preferred embodiment, the microprocessor 10 of FIG. 1is fabricated on a single silicon substrate using complementarymetal-oxide-semiconductor (CMOS) processing. Any one of many well-knownCMOS processes may be employed, however, it will be obvious that thepresent invention may be realized with other technologies, for instance,n-channel, bipolar, SOS, etc.

In FIG. 1, the single chip microprocessor 10 includes a bus interfaceunit 14, instruction decoder unit 16, execution unit 18, addresstranslation unit 20, and the subject of the present invention, thebreakpoint circuit 30 which is included within unit 20. The 32-bitmicroprocessor is shown coupled to an external random-access memory 13.The bus unit 14 includes buffers for transmitting the 32-bit address andfor receiving and sending the 32 bits of data. Internal to themicroprocessor, the bus unit includes a prefetch unit for fetchinginstructions from the memory 13 and a prefetch queue which communicateswith the instruction unit of the instruction decoder. The queuedinstructions are interpreted and queued within unit 16. The arithmeticlogic unit of the execution unit 18 in general executes theinstructions.

For the illustrated microarchitecture, the address translation unitprovides two address translation functions; one associated with thesegment descriptor registers and the other with the page descriptorcache memory. It is linked to the bus interface (14). These functionsare described in detail in copending application, Ser. No. 744,389,filed Jun. 13, 1985, entitled MEMORY MANAGEMENT FOR MICROPROCESSORSYSTEM, and assigned to the assignee of the present invention. Thebreakpoint circuit is coupled between the segment descriptor registersand the page descriptor cache memory on the bus 19. The virtualaddresses are transmitted over this bus. These virtual addresses arereadily accessible to a programmer but the physical addresses are not.It is difficult to provide breakpoints based on physical addresses, asmentioned.

A control unit (not illustrated) is coupled to the units of FIG. 1 toprovide overall control.

In FIG. 2, the breakpoint circuit 30 of FIG. 1 includes a 32-bitregister and comparator 34. In the presently preferred embodiment, theregister and a comparator are incorporated in a single circuit; onestage of this register/comparator is shown in FIG. 3. Theregister/comparator 34 stores the predetermined address at whichbreakpoints are to occur, hereinafter sometimes referred to asbreakpoint addresses. The register/comparator 34 compares the storedbreakpoint address with the virtual address generated by themicroprocessor, hereinafter sometimes referred to as the current virtualaddress or current address. When the load signal 35 is present, a 32-bitbreakpoint address is loaded over bus 19a into the register/comparator34. Thereafter, the register/comparator 34 compares the breakpointaddress with each current address on the bus 19 and when a match occurs,provides a "hit" signal on line 46. The two least significant bits ofthe breakpoint address in the register/comparator 34 are not used aspart of this comparison for reasons which will be explained, but rather,are coupled to the programmable logic array (PLA) 38.

The instruction decode unit 16 of FIG. 1 interprets a predeterminedinstruction to the microprocessor as a load register/comparator 34command and permits the user to thereby load register/comparator 34 withthe breakpoint address. Another instruction allows the address stored inregister/comparator 34 to be read by the user.

In the currently preferred embodiment, four register/comparators 34 areused allowing four different breakpoint addresses to be stored. For eachregister/comparator 34, there is an accompanying register 32, allowingfor storage of control bits for each breakpoint address as will beexplained. For purposes of explanation, the circuit of FIG. 2 is treatedas having only a single first register/comparator 34 and a single secondregister 32. It will be obvious, however, to one skilled in the art thatany number of register/comparators 32 and register 34 may be employed,thereby permitting interruption at any one of a plurality of breakpointaddresses.

The control register 32 stores four control bits for each breakpointaddress. One bit determines whether the breakpoint address represents areference to data or to the computer program. In the cases of areference to data, two control bits are used to determine the width ofthe breakpoint. In the currently preferred embodiment, the breakpointmay be 1, 2 or 4 bytes wide. Again, for data breakpoints, anothercontrol bit is used to permit interruption at either read-cycles only orread or write cycles. As is the case with register/comparator 34, apredetermined instruction to the microprocessor 10 is interpreted by theunit 16 to allow the user to load register 32. This may be the sameinstruction used to load register/comparator 34.

The enable logic circuit 36 is coupled to receive bus control signals.These lines contain the control signals which determine whether acurrent address is a reference to program or data; and, in the case ofdata references, whether it is a read cycle only or read or write cycle.The enable logic circuit 36 compares these control signals with two ofthe control bits from register 32 and if the memory cycle matches thatselected by the user, an enable clock is generated to the AND gate 40.Ordinary logic circuits are used for this purpose.

As mentioned, the breakpoint may be 1, 2 or 4 bytes wide and this userselected width is stored in register 32. The two bits required for thisselection are coupled to the PLA 38. Additionally, as mentioned, the twoleast significant bits stored in register/comparator 34 are coupled tothe PLA 38. Timing and control signals from lines 20 are also coupled tothe PLA 38. The PLA is not user programmable but rather is permanentlyprogrammed at manufacture. The PLA implements the logic set forth in thesubsequent paragraph. The use of a PLA is not critical to the presentinvention, that is, other logic circuits may be used in lieu of the PLA.The PLA provides a signal to gate 40 when a "match" occurs.

Referring to FIG. 4a, a relatively wide breakpoint address reference 70is illustrated (e.g., 4 bytes). The current memory virtual address mayreference only a portion of the reference 70. For the case of a narrowbreakpoint address reference as shown in FIG. 4b, as reference 74, arelatively wide virtual address reference may encompass the narrowerbreakpoint address reference 74. The two cases shown in FIG. 4a and FIG.4b are resolved by the PLA 38. As mentioned, ordinary logic circuits maybe used to determine if the current memory address reference fallswithin a wide breakpoint address reference, or if a narrower breakpointaddress reference falls within a wider current memory address reference.If either of these conditions occur, a "match" signal is provided online 52.

The AND gate 40 receives three inputs, the hit signal fromregister/comparator 34, enable clock from logic circuit 36 and the matchsignal from circuit 38. The hit signal is generated when the 30 mostsignificant bits of the current virtual address match the 30 mostsignificant address bits of the stored breakpoint address. The output ofgate 40 provides the breakpoint signal which is used to interrupt theoperation of the microprocessor.

The illustrated single stage of register/comparator 34 shown in FIG. 3includes a static memory cell 53 and a comparator 54. Bus lines 19a and19b carry a single address bit and its complement. The hit line 46 isshown coupled to the comparator 54 and to a p-channel transistor 56.This transistor is used to precharge line 46 prior to each virtualaddress bus cycle. Line 46 is coupled to the other stages of theregister/comparator 34.

The cross-coupled inverters form an ordinary flip-flop or static memorycell 55. This cell is loaded from lines 19a and 19b when the load signalis present on line 35. Once the register is loaded, the load signaldrops in potential effectively decoupling the cell 55 from lines 19a and19b. Thereafter, when the current virtual address appears on these linesand the φ1 signal is present, the contents of cell 55 are compared withthe address on the bus 19 by the comparator 54. If any of the 32-bitpairs which are compared do not match, line 46 is discharged preventingthe AND gate 40 of FIG. 2 from being enabled. The circuit of FIG. 3 isdescribed in more detail in the above-mentioned application where thecircuit is used as part of a content addressible memory.

In use, the user determines up to four breakpoint addresses, and selectswhether the addresses are references to program or data, and in the caseof data references the width of the reference and whether the breakpointis to occur on a read cycle only or read or write cycle. Through aparticular instruction, the user is then able to load up to fourbreakpoint addresses in register/comparator 34 and set the correspondingcontrol bits for each breakpoint in register 32. Then during eachvirtual address bus cycle, a comparison occurs within theregister/comparator 34 and the logic circuits 36 and 38 determine if theuser selected conditions exist. If the addresses match and conditionsmatch, then a breakpoint signal is generated at gate 40.

Unlike the prior art methods described, a real time breakpoint signal isgenerated. The comparisons occur while the virtual address is present onthe bus, and since there is very little propagation delay, the interruptsignal can be generated at the appropriate time.

Thus, an improved breakpoint apparatus has been described. The apparatusis particularly useful for single chip microprocessors where virtualaddresses are translated to physical addresses "on-chip".

I claim:
 1. In an integrated circuit microprocessor which includesaddress generation circuitry for generating virtual addresses forreference to program instructions and data, address translationcircuitry for converting said virtual addresses to physical addresses,an interpretation unit for interpreting program instructions, and anarithmetic unit for operating upon data in accordance with interpretedinstructions, an improvement for providing a breakpoint signalcomprising:a first register for storing a virtual address, whichdetermines where a breakpoint is to occur, said virtual addresshereinafter referred to as a breakpoint address, said first registerbeing loaded using a predetermined instruction interpreted by saidinterpretation unit; a second register for storing control bits, whichdetermine conditions when said breakpoint is to occur, said secondregister being loaded using a predetermined instruction interpreted bysaid interpretation unit; and breakpoint circuitry for generating saidbreakpoint signal, said breakpoint circuitry comparing at least aportion of said breakpoint address from said first register with atleast a portion of a current virtual address, said breakpoint circuitrycoupled to said second register to sense at least one of said storedcontrol bits which determines if a breakpoint is to occur when saidcurrent virtual address is a reference to data or to programinstructions, said breakpoint circuitry also coupled to receive buscontrol signals providing an identification of whether said currentvirtual address is a reference to data or to program instructions, saidbreakpoint circuitry generating said breakpoint signal when said currentvirtual address is an address where a breakpoint is to occur and whensaid at least one of said control bits matches said indentification;said first and second registers and breakpoint circuitry providing areal time breakpoint signal to said microprocessor.
 2. The improvementaccording to claim 1 wherein said second register stores control bitsincluding an indication of a data width for said breakpoint address. 3.The improvement according to claim 1 wherein said second register storescontrol bits including an indication of whether a breakpoint is to occuron a reference to data during a read cycle only or a read or writecycle.
 4. The improvement according to claim 1 in combination with amemory external to said microprocessor, said memory for storinginstructions and data referenced by said physical address.
 5. Theimprovement according to claim 1 including a plurality of registers forstoring breakpoint addresses at which breakpoints are to occur, saidfirst register being one of said plurality of registers.
 6. In anintegrated circuit microprocessor which includes address generationcircuitry for generating virtual addresses for reference to programinstructions and data, address translation circuitry for converting saidvirtual addresses to physical addresses, an interpretation unit forinterpreting program instructions, and an arithmetic unit for operatingupon data in accordance with interpreted instructions, a process forproviding a real time breakpoint signal to said microprocessor, saidprocess comprising the steps of:providing a first register for storing avirtual address where a breakpoint is to occur, said virtual addresshereinafter referred to as a breakpoint address, said first registerbeing loaded using a predetermined instruction interpreted by saidinterpretation unit; providing a second register for storing controlbits defining conditions when a breakpoint is to occur, said controlbits defining if a breakpoint is to occur when said breakpoint addressis a reference to data or to program instructions, said second registerbeing loaded using a predetermined instruction interpreted by saidinterpretation unit; receiving a current virtual address; receiving abus control signal indicating whether said current virtual address is areference to data or to program instructions; comparing at least aportion of said breakpoint address from said first register with atleast a portion of said current virtual address; comparing at least aportion of said control bits from said second register with said buscontrol signal; and generating said breakpoint signal when,i) said atleast a portion of said breakpoint address from said first registermatches said at least a portion of said current virtual address, and ii)said at least a portion of said control bits from said second registermatches said bus control signal.
 7. The process according to claim 6wherein said second register stores control bits including an indicationof a data width for said breakpoint address.
 8. The process according toclaim 6 wherein said second register stores control bits including anindication of whether a breakpoint is to occur on a reference to dataduring a read cycle only or a read or write cycle.
 9. The processaccording to claim 6 wherein instructions and data referenced by saidphysical address are stored in a memory external to said microprocessor.10. The process according to claim 6 further including a step ofproviding a .[.second.]. .Iadd.third .Iaddend.register for storing adifferent breakpoint address at which a different breakpoint is tooccur.